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Design optimization of processvariation tolerant spoof surface plasmon polariton interconnect for chip-to-chip communication

by Faizul Bari, Md.

Publisher: Dhaka Department of Electrical and Electronic Engineering, BUET 2020Description: xi, 66 p.Subject(s): Data transmission systemsOnline resources: Click here to access online

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Item type	Current location	Call number	Copy number	Status	Date due	Barcode
Thesis	Central Library, BUET Reference section	623.8/FAI/2020 (Browse shelf)	1	Available		117618

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Previous	623.8/ASA/2017 Enhancement of ethernet ring protection switching protocol for improving performance of carrier networks	623.8/ASA/2021 Cross-talk analysis of spoof surface plasmon polariton interconnects for ultrafast chip-to-chip communication	623.8/DEV/1987 Developing world communications	623.8/FAI/2020 Design optimization of processvariation tolerant spoof surface plasmon polariton interconnect for chip-to-chip communication	623.8/FRE/1981 Telecommunication transmission handbook	623.8/HAS/2024 Design and analysis of a highly sensitive simple microstructured surface plasmon resonance biosensor	623.8/INT/2018 Communications	Next

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