Abstract:
MOSFETs are used extensively In very large scale integration (VLSI)
Technology specially In vanous digital circuits such as 11lIeroproeessor.
semiconductor memories etc. Since the birth of Integrated Circuits (lC)
fabrications the need for the reduction of device dimensions is driven by the
requirement that Ie of high complexity can be fabricated. The purpose of micro
miniaturization of the MOSFET is not only to increase the packing density but
also to improve the circuit performance at the same time. The fundamental issue
of downsizing the MOS transistor is to preserve the long channel characteristics
after miniaturization. But as the dimension of the MOSFET is reduced.
departure from the long channel behavior occurs due to various undesirable
short channel effects.
The threshold voltage V1h,for fully depleted MOSFETs with effective channel
lengths down to submicrometer range has been investigated. In this thesis. a
simple quasi-two-dimensional model is used. taking into account thc effect of
gate oxide thickness, source/drain junction depth and channel doping. to
describe the accelerated V'h roll-off and drain voltage depcndcncc. Thc
proposed model retains accuracy because it docs not assume "priori charge
partitioning or constant surfacc potential. Also it is simple in fimctional form
and hence computationally efficient.
