Analytical modeling of threshold voltage of Deca-nano n-MOS transistor

Abstract

The conventional threshold voltage model is derived for the homogeneous doping concentration. As the channel length of MOSFETs is scaled down to deep-submicrometer or sub-lOO nm regime, we observe short-channel effects, such as, steep threshold voltage roll-off, increased off-state leakage current and bulk punch-through. The short channel effects arise as results of two dimensional potential distribution and high electric fields in the channel region. Lateral channel engineering utilizing halo or pocket implant surrounding drain and source regions is effective in suppressing short channel effects. An extension of the homogeneous model to the nonhomogeneous impurity pileup in the vertical direction has been reported previously. However, the reported model cannot be extended further to the pocket implantation, where inhomogeneity along the channel is the main cause for the reverse short channel effect. A strong reverse short channel effect suppresses the short channel effect on threshold voltagc of the MOSFET. Another threshold voltage model for pocket implanted MOSFETs with resolving circuit simulation based on simplified pocket implanted profile, does not describe. the case of sub-lOO nm. Extrapolation of the threshold voltage versus gate length curve cannot predict the threshold voltage accurately. Therefore, we propose a threshold voltage model that describes the threshold voltage for the gate length down to 50 nm. Advanced MOSFETs are nonuniformly doped as a result of complex process flow. Thcrefore, one of the key factors to model threshold voltage (VII,) accurately is to model its non-uniform doping profile of the MOSFET. The focus here is to transform the lateral l-D pocket profile across the channel to an effective doping concentration expression that can be applied directly to the V1h expression incorporating V1h shift due to short channel effect in the model to suppress the short channel effect. There are other pocket profiles found in the literature, such as, Gaussian distribution, hyperbolic cosine profile etc. for the threshold voltage model of the MOS devices. Our simulation results are compared with the simulation results using these pocket profiles for various device and pocket profile parameters. The comparison shows that the proposed model has a simple compact form that can be used to study and characterize the pocket implanted advanced ULSI devices down to 50 run gate length . .It also proves the validity and usefulness of our proposed model of the threshold voltage for circuit simulation. Our model is also compared with experimental data.