Abstract:
A new architecture to realize a modular, high-speed, reconfigurable, digital Rank Order Filter
is designed and developed in this work. A bit-level algorithm by Kar and Pradhan has been
modified to implement the Filter. Using the designed Rank Selection Circuit it is possible to
find the element of a certain rank in a given sequence of N elements in each window in M
steps, where M is the number of bits used in binary representation for the elements of the
sequence. To implement the circuit N number of identical Bit Update Circuit, a Parallel
Counter circuit and a Comparator circuit are required.
The throughput of the designed Rank Order Filter is not satisfactory though it can work at a
very high clock speed. The throughput of the Rank Order Filter depends on the bit length of
the input samples and every A.l' clock pulse a rank element can be obtained as output, where
M is the bit length of the input samples. In this work using parallel processing technique the
throughput of the circuit is increased by M times. So with every clock pulse a rank element
can be obtained as output from the modified ROF. The simulation results of the circuit is
found correct and satisfactory.
Special cases of Rank Order Filter are Maximum, Minimum and Median Filter. They are the
most popular Filters and due to their importance, in this work the architecture of the designed
Rank Order Filter is modified to implement these filters efficiently using less numbcr of
transistors. In Maximum and Minimum Filters the Parallel Counter circuit and the
Comparator circuit can be eliminated by only an OR and an AND gate respcctively and in
case of Median filter substantial minimization of the Rank Order Filter circuit is achieved if
the window size of the filter is 2"_1, where n is an integer.
All the Rank Order Filters designed in this work is verified by implementing them in FPGA
The transistor level HSPICE simulation result of all the Rank Order Filters are also shown.
Rank selection by the designed ROF circuits from HSPI CE simulation shows a very good
agreement with that obtained by FPGA. The layout design of the 5-input reconfigurable Rank
Order Filter is also done in this work. From the layout design, the netlist is extracted for
further simulation in HSPICE. The HSPICE simulation using extracted netlist is compared
with the result that obtained in schematic level simulation. Desired rank selection from both
the simulation are found correct, however when the extracted netlist is simulated the speed of
the circuit is found to decrease due to the delays caused by interconnection capacitances.
The number of logic gates required to implement the BUC of the proposed Rank Order Filter
is less by almost 50% compared with the other BUCs implemented in earlier works. Thc
Comparator circuit also requires less number of logic gates than conventional Comparator
circuit. The new architecture of the designed Rank Order Filter is found to operate at a very
high clock speed. The modified Rank Order Filter with increased throughput also requires
less number of Bit Update Circuit and Shift registers for their implementation.
Thus, this thesis work has yield a small size, reconfigurable, reliable, low power consuming
and fully digital Rank Order Filter for digital signal processing.
