Impact of multiple gate bias on the capacitance - voltage (C - V) characteristics of thin - film fully depleted four gate transistor

Abstract

The impact of the back gate and the junction gate biases on front gate Capacitance-Voltage (C ~ V) characteristics of the fully depleted (FD) Four Gate Transistor (G4-FET) has been studied by means of systematic semi-classical 2-D simulations. It has been revealed that in strong inversion and strong accumulation of the front interface, back gate bias does not have significant effect on C - V. However, in weak inversion, weak accumulation and depletion, the back gate bias has significant effects. An accumulation/inversion channel at back gate retards zero capacitance to be achieved. A very strong inversion/accumulation channel of back gate cannot be mitigated by applying front gate bias, that is zero capacitance cannot be achieved unlike in case of a usual fully depleted device. A weaker inversion at the back gate causes the region of zero capacitance to become smaller. The effect of junction gate bias has been found to be more interesting. In accumulation region of the front gate, the greater the junction gate voltage, the smaller the capacitance at a particular front gate voltage. In other words, accumulation is easily achieved if junction gate bias is lower. In inversion and depletion of front gate, an opposite phenomenon is exhibited. In this case, capacitance increases with junction gate voltage. That is, inversion is easily achieved if junction gate bias is higher. Thus, a higher junction gate voltage assists inversion, while retards accumulation. The effects of back gate bias are found to be independent of junction gate bias and vice versa. Thus, it is concluded that back gate and junction gate biases have significant influence on front gate capacitance.