Abstract:
Electrical instability is one of the major concerns regarding high-K-based field-effect
transistors (FETs); threshold-voltage (VT) shifts observed in pulsed measurements
is considered to originate from the tunneling of channel electrons into traps in the
gate dielectrics. Although some experimental models done by previous researcher
are useful for providing qualitative explanations, a device-level numerical model is
nonetheless necessary to quantitatively analyze the origin and impact of the
electrical instability in such multi stack systems. The charge trapping/detrapping
model to analyze the gate threshold voltage instability reported so far have been
using detrapping of the trapped charges back to the channel alone ignoring the
detrapping to the gate. But a complete quantum mechanical is necessary to observe
the behavior of charge trapping and threshold voltage instability. In this context,
a quantum mechanical model (QM) is presented for analyzing the threshold voltage
instability induced by charge trapping/detrapping for the inversion gate capacitance
of MaS structures with high-k gate dielectrics. The threshold voltage shifts are
modeled based on a modified rate equation and the properties of carriers in inversion
layers are studied by solving coupled SchrOdinger's and Poisson's equation self
consistently. The model incorporates the effects due to detrapping of charges to the
gate region which has been taken as negligible before. The accuracy of the model
has been verified with some reported experimental results. It is evident from the
results that, not only the further shrinking of Effective Oxide Thickness (EaT) but
also increasing gate pulse width influence the detrapped charges that play a
significant role in the threshold voltage instability. And these detrapped charges to
the gate region also increase the gate current of the MaS devices, which is under
estimated if calculated without considering these charges.
