Study of the anomalous threshold voltage of a short - Channel mosfet

Abstract

MOSFETs in integrated circuits have become smaller and smaller in order to achieve higher packaging density and to reduce cost. Reducing channel length of a MOSFET leads to undesirable effects in device characteristics. In order to get higher performance MOS devices, the modern fabrication technologies such as gate polysilicon, lightly doped drain (1DD) structure, heavy doping at the edge of the channel by halo ion implantation, very lightly doped region at the edge of the source/drain junction at the boundary to the channel by salicidation process and formation of salicide simultaneously in the source, drain and polysilicon gate regions are used. Also overlapping of gate to the source and drain junctions are avoided so that stray capacitance does form at the gate-drain and gate-source regions. All fabrication techniques mentioned above result the potential barrier at the source and/or drain junction to the boundary of the surface channel. This potential barrier can severely degrade the drain current and transconductance of the device. Also, this barrier causes increased threshold voltage as the channel length of the device is decreased. As the behaviour of the device deviates from its normal characteristics, the resulting phenomena'is known as anomalous behaviour of short-channel MOSFET. In this thesis the I-V characteristics and transconductance of short channel device have been modeled by considering tile barrier potential both in the subthreshold and active regions incorporating the physics of the anomalous behaviour. The results have been compared with the long-channel MOS behaviour.