Design of a high speed crypto-processor ASIC for next generation IT security

Abstract

Since demand for privacy and security of information are gradually emerging due to the rapid growth of information and communication technology, the research in protecting information for coming generation is gelling enormous importance. Cryptographic algorithms form the fundamental aspect within this research field. The Advanced Encryption Standard (AES), the latest security algorithm, has added new dimension to cryptography with its potentiality of safeguarding the IT systems. Since the National Institute of Standards and Technology (NIST) accepted the AES to be the next generation IT security algorithm, a lot of research is going on to harness the power of AES in different security applications. For applications requiring high speed, hardware based implementation is the only choice. Since Application Specific Integrated Circuit (ASIC) is inherently ornamented with better performance than any other discrete system, ASIC based AES crypto-processor is anticipated to be the best solution for high-speed security mechanism. This thesis presents the design of a crypto-processor ASIC to generate cryptographically secured information at a rate of multi-ten Gbps. The proposed novel crypto-processor addresses the next generation IT security requirements: the resistance against all attacks and high speed with low latency. This thesis uses AES algorithm as AES meets the first requirement, i.e. it is immune to all known attacks. Achieving high speed with AES algorithm is the main goal of this thesis. This work optimizes AES algorithm to eliminate algebraic operations from the datapath, which contributes to increase the processing speed and reduce the latency. By using loop unrolling, inner-round and outer-round pipelining techniques and offline key scheduling, this design can deliver secured data at ultra high speed. Thus, it becomes available for encryption on an optical link. The prc'posed crypto-processor is designed with Verilog HDL using Quartus II EDA software. The design is then simulated on a Stratix II GX FPGA device to test and verify the functional behavior and performance of the crypto-processor. The speed achieved on the FPGA is 36.16 Gbps. This design can be used to process data at a lhroughput of about 100 Gbps on ASIC technology.