Abstract:
The focus of this thesis is to design a silicon based RF frequency synthesizer in CMOS process that will generate frequency from the S band up to the X band (2 GHz -12 GHz). To achieve this target, an improved CMOS ring oscillator topology is proposed and is implemented in IBM 90nm RF CMOS process technology. The other building blocks of a frequency synthesizer, namely phase frequency detector (PFD), charge pump (CP), and divider circuits were also designed and implemented successfully to achieve the target. The proposed VCO can generate frequency from 2.51 GHz to 12.68 GHz with almost constant gain (Kvco) and low phase noise within the operating range. The performance of PFD has been boost up with proposed technique and an innovative idea in the design of CP has reduced the glitches in the charging and discharging current of the loop filter.
Each block of the proposed Phase-Locked Loop based Frequency Synthesizer is designed using Cadence Electronic Design Automation tools in IBM 90nm CMOS process technology. Virtuoso Schematic Editor tool is used for schematic design and all the simulation results are plotted in Cadence Spectre. Virtuoso Layout Editor (XL) tool is used for physical layout design whereas Assura DRC, LVS, and QRC tools are used for physical verification.
Simulation results are provided for the performance of VCO, PFD, CP and the PLL. Post-layout simulation including the parasitic is also provided to verify the functionality of the proposed circuit. Pre and post layout simulation results are compared and it is found that they meet our target and specification.
Finally, the results obtained for the designed circuits are compared with the literature works and is found that our proposed circuits are better in most of the performance parameters than those reported in literature works.
