General purpose simulator for network on chip

Abstract

It is predicted that future integrated circuits that will contain more than one billion transistors will allow much more complex designs than possible today. System on Chip (SoC) design involves the integration of such numerous heterogeneous semiconductor intellectualproperty (SIP) blocks. The success of this approach depends on the seamless integration of cores like processors, memories, Universal Asynchronous Receiver Transmitters(UART),etc. Someof the main problemsassociatedwith futureSoCdesign arise fromnon-scalableglobal wire delays,failureto achieveglobal synchronizationwith a single clock, errors due to signal integrity issues, on-chip communication delays and difficulties associated with nonscalablebus- basedfunctionalinterconnects.One approach to address these problems is to make a Network on Chip (NoC) that handles communication over the chip using a variant of traditional network communications. This research describes a general purpose Network on Chip simulator, which is capable of simulating various topologies. The implementation details of the simulator have been described. The assumptions about the network setup and simulation environment and parameters are also described. The external and internal configuring processes are also described. The switching techniques and details of some routing algorithm for NoC are described with examples. The simulator is based on some of the OSI reference model layers, with the layers individually represented as exchangeable modules. A suitable model of execution and a hierarchical model of a NoC have been designed and implemented. The implemented general purpose simulator can be configured for any topology and routing algorithm to measure vanous performance parameters. Both synchronous and asynchronous communications are supported in this simulator. The IP nodes can be configured to wide range of different clock rates different than that of the NoC switches. The extensive simulation result for various topologies and various network configurations are analyzed.