Abstract:
This thesis contains the technical details of the design, development and construction of an 8086-based
16-bit microprocessor trainer. The trainer has been built using local technology and at lesser cost
compared to the foreign made trainer3. The hardware and software design are simple and logical to allow
others become acquainted with the design rules. The trainer has been built with the features of a
'Learning and Development System.' The features are (a) edge connectors for developing interfacing
circuits, (b) integrated peripheral module containing all the common peripheral controllers (c) the IBMPC
to trainer down loading software and (e) many useful routines and subroutines in the EPROMs.
The trainer has been constructed successfully. All the objectives quoted above have also been achieved.
The trainer has the following hardware features: (a) 8086 CPU, (b) 64Kbytes EPROM, (c) 64 Kbytes
RAM, (d) Bus Lines at Edge Connectors for Interfacing Experiments, (e) 5.5"x2.5" Bread Board for
Prototyping Circuits, (I) Well-documented User's Manual, (g) 18-Key Hex-key pad for Machine Codes
Programming, (h) 9 - Digits 7-Segment Display Window, (i) Memory and Port Decoded Lines Available
at Edge Connectors, (j) +5V Power Supply Adapter.
The trainer has also software features like (a) Powerful and Comprehensive Resident Monitor Progra.m,
(b) Auto/Manual Data Entry for both Bytes/Word Operations, (c) Program Execution Capability, (d)
Forward/Backward/Change/BackspaccFacilities, (e) Bytes/Word Examine/Edit Capability, (I) Single
Instruction Execution Capabiliiy for Program Debugging, (g) Basic Initialization Routines for Many
Peripheral ICs like ADC, DAC,825 I ,8259, (h) Register's Contents can be Examined and Changed, (i)
Flag Register's Contents can be Examined in Bit-form and Hex-form, (j) Many Stand-lone Useful
Routines and Subroutines to facilitate microprocessor based system design.
This thesis contains detailed description of the procedures and techniques employed for the design,
development and construction of the trainer. It is a comprehensive reference containing experimented
steps that the designers and academicians may consult to solve microprocessor related problems. This
thesis has also documented the description of the new ideas conceived to solve varieties of hardware and
software problems. The examples are -- the design of composite memory/port decoder and single
stepping routine.
The thesis contains 10 chapters, 6 appendices and a reference caption. Attempt has been made to
document the work in the form of descriptive language, schematic diagram, flow chart, assembly and C
codes.
