Performance analysis of multiprocessors sharing memory modules connected by multibus network

Abstract

With the availability parallelism through fast physical devices, of the high hardware between processor and memory modules is required to be efficient enough for high performance of a multiprocessor system. For higher performance multiple bus interconnection can be used. In this thesis work multiple bus interconnection is used for processor memory interconnection in multiprocessor system. Multiple bus connection is fault tolerant and during a bus fault only system performance decreases by a little amount and there remain patmto every memory module from each of the processors. Equal priority, unequal priority and a combination of unequal priority and random delay protocols are used for resolving bus and memory conflicts. Both synchronous and asynchronous timing and packet switched and circuit switched systems are simulated for performance analysis. For performance analysis parameters used are average queue length, processor .utilization, memory bandwidth and bus utilization. Hardware design of synchronous and asynchronous arbiters are presented. In synchronous design equal priority protocol is assumed. In asynchronous system a two level unequal priority protocol is examined. Simulation result is validated "by analytical solutions.