Abstract:
CMOS is one of the leading VLSI technologies today. It is being used to implement high
performance circuits in VLSI. Conventional static CMOS logic is attractive because of its
extremely low quiescent power dissipation. This makes its power-delay product favorable.
compared to those of other technologies, viz., bipolar and nMOS technology. Although, the
advancement of integrated circuit technology has now made it possible to fabricate devices with
sub-micron dimensions thereby leading to very high speed CMOS circuits, the speed of CMOS
devicesis stilllower than its nMOS counterpart.
Differential Cascode voltage Switch (DCVS) logic and Differential Split-Level (DSL)
CMOS logic were introduced for speed improvement in CMOS circuits. However, these CMOS
circuit techniques have not been used so far to design real VLSI chips owing to some inherent
problems. This thesis examines the performance of the differential CMOS circuits compared to
conventionalstaticCMOS with a view to determinetheir suitabilityfor VLSI implementation. The
results obtained show that static DCVS circuits are slower than conventional static CMOS while
DSL circuits are faster at optimum reference voltage only when short channel logic n-transistors are
used.
