DSpace Repository
Calculation of trapped charge in the silicon dioxide layer of an enhancement type MOSFET using impurity trap levels
JavaScript is disabled for your browser. Some features of this site may not work without it.
| dc.contributor.advisor | Khan, Dr. M. Rezwan | |
| dc.contributor.author | Saiful Islam, Syed | |
| dc.date.accessioned | 2016-06-22T04:20:55Z | |
| dc.date.available | 2016-06-22T04:20:55Z | |
| dc.date.issued | 1996-04 | |
| dc.identifier.uri | http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3337 | |
| dc.description.abstract | For abstracts please see full text | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Department of Electrical and Electronic Engineering, BUET | en_US |
| dc.subject | Calculation - Trapped charge - Silicon dioxide layer - Enhancement - MOSFET- Impurity trap - Level | en_US |
| dc.title | Calculation of trapped charge in the silicon dioxide layer of an enhancement type MOSFET using impurity trap levels | en_US |
| dc.type | Thesis-MSc | en_US |
| dc.contributor.id | 921312 P | en_US |
| dc.identifier.accessionNumber | 89561 | |
| dc.contributor.callno | 623.815/SAI/1996 | en_US |
Files in this item
This item appears in the following Collection(s)
-
Dissertations/Theses - Department of Electrical and Electronic Engineering
Post graduate dissertations (Theses) of Electrical and Electronic Engineering (EEE)