Design of C-testable carry save array multiplier using VHDL

dc.contributor.advisor	Harun -ur-Rashid, Dr.
dc.contributor.author	Masud Uddin Bhuiyan, Mohammad
dc.date.accessioned	2016-06-27T03:30:06Z
dc.date.available	2016-06-27T03:30:06Z
dc.date.issued	2005-02-15
dc.identifier.uri	http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3384
dc.description.abstract	For abstracts please see full text	en_US
dc.language.iso	en	en_US
dc.publisher	Department of Electrical and Electronic Engineering, BUET	en_US
dc.subject	Integrated circuits - Very large scale integration	en_US
dc.title	Design of C-testable carry save array multiplier using VHDL	en_US
dc.type	Thesis-MSc	en_US
dc.contributor.id	100106220	en_US
dc.identifier.accessionNumber	100820
dc.contributor.callno	623.95/MAS/2005	en_US