Development and analysis of a dual stack approach for low leakage and high performance VLSI design

Abstract

The main objective of this thesis is to provide new solutions to reduce leakage power for Very Large Scale Integration (VLSI) designers. Especially, we focus on leakage power reduction. Although leakage power was negligible at 0.18μ technology and above, in nanoscale technology, such as 0.07μ, leakage power is almost equal to dynamic power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. In this thesis we propose a new technique to reduce leakage power with minimum area. It is a state saving technique which makes it better than traditional sleep transistor technique. As it is a state saving technique, it can be used in memory design i.e. SRAM (Static Random Access Memory) cell. Although the proposed approach incurs some delay, the SRAM cell with proposed method can achieve ultra-low leakage power consumption while suppressing two main leakage paths in an SRAM cell. Unlike the stack approach (which saves state), this approach can work well with dual-Vth technologies, reducing leakage by several orders of magnitude over the stack approach in single-Vth technology. In comparison with the most common approaches in VLSI design (sleepy stack, dual stack and dual sleep approaches), the proposed method shows better leakage power(almost 50% leakage reduction than dual stack and 70% leakage reduction than dual sleep) and dynamic power dissipation than dual stack, dual sleep, sleepy stack and better speed than sleepy stack, dual sleep. Moreover, the area required by proposed method is much less than those of the sleepy stack and dual stack approaches.