Modeling and performance analysis of semiconductor on insulator field effect transistors

Abstract

Due to aggressive scaling of Metal Oxide Semiconductor Field Effect Transistors (MOSFET), Silicon (Si) technology is expected to reach its physical performance limit within few years. Researchers are looking for alternative materials, and alternative architectures for future logic and information processing devices. Ultrathin body (UTB) fully depleted (FD) Semiconductor on Insulator is one of the promising architecture for next generation devices due to its superior performance in terms of junction capacitance and subthreshold swing. Si has been explored as a channel material in Semiconductor on Insulator devices, known as Silicon on Insulator (SOI) MOSFETs. Moreover, III-V materials and Ge are being studied extensively as good candidates to replace Si as channel material due to their high electron and high hole mobility respectively; light electron and light hole conduction effective mass respectively. In this dissertation, we mainly have focused on two issues. First, A physically based compact surface potential model is proposed to simulate gate C-V characteristics of UTB FD SOI devices. Quantum mechanical (QM) effects, such as, energy quantization of inversion layer carriers, wavefunction penetration into the front and buried oxide layers are incorporated in this model. The power law for lowest (ground) quantized energy level versus normal electric field at oxide (E1 _ Fox ) is used with = 0.64 for electrons and = 0.6 for holes in weak and strong inversion region. Surface potentials at three interfaces (front oxide - silicon film interface, silicon film - buried oxide interface and buried oxide - substrate interface) are calculated using the E1 values. Substrate region is incorporated in the calculation to simulate devices with low substrate doping. Once surface potentials at the three surfaces are know, inversion and depletion charges determined to calculate gate capacitance. Computed compact C-V characteristics are compared with self-consistent Schr¨odinger - Poisson simulation over a range of device parameters to verify the accuracy of the model. Second, Ballistic performance of III-V on Insulator (III-V-OI) and Ge on Insulator (GeOI) devices with high - gate dielectrics have been investigated as possible replacement in future CMOS technology as n- and p-type MOSFETs respectively. InAs and GaAs are investigated as possible replacement for Si in n-MOSFET due to high electron mobility and light conduction effective mass of electron. Ge is investigated as possible replacement for Si in p-MOSFET due to high hole mobility and light conduction effective mass of hole. Numerous experimental research have been conducted on IIIV- OI and GeOI, and huge performance improvement has been reported. However, all these devices are semiclassical devices whose transport is drift - diffusion (DD) type. In this dissertation, we investigated the performance of scaled III-V-OI and GeOI devices whose transport mechanism will be ballistic. To determine the ballistic drain current, electrostatics of the devices are determined using self-consistent Schr¨odinger - Poisson simulation. Once the electrostatics is known for a specific gate bias ballistic current is calculated using the over-the-barrier transport model. Significant performance enhancement is found in both III-V-OI and GeOI devices compared to SOI devices.