Design and analysis of an active low loss technique for series electrolytics to maintain high DC bus voltage of a converter

Abstract

In this thesis, analysis of an active low loss approach to maintain the DC voltages across series connected electrolytic capacitors used in a converter is presented. The proposed design mitigates the impact of leakage current dispersion, which causes voltage imbalance among capacitors. In traditional method, a passive balancing circuit is often used, where balancing resistors are usually connected in parallel with the capacitors. However, the current flowing through the resistors is much higher than the leakage current of the capacitors and cause high dissipative loss. An active balancing circuit is proposed in this thesis, which ensures the capacitor voltages at desired values without unreasonable increase in the power loss. The circuit is designed using both two and four electrolytic capacitors in series connection to divide the dc bus voltage. For the ease of design and analysis, an application of both two and four equal voltages across capacitors is considered. Here, the control circuit is designed using op amps to compensate the voltage imbalance occurred among capacitors. Simulation results for impacts of various leakage currents as well as load variation and improvements after applying the proposed technique are discussed.