Abstract:
Traditional analog energy metcrs arc unable to copc with the rapidly
changing load and cannot measure energy consumed by high frequency harmonic
contents of the power. Singlc phase digital energy meters havc bccn devcloped for
this purpose but these use separate energy calculation chip and other pcripheral
chips. These make the meter largc in size and costly. Besides, these meters arc
unable to measure the quality of powcr. This thesis prcsents a complete digital
design of a three phasc energy meter in a singlc Ficld Programmable Gate Array
(FPGA) chip with additional capability to measure the quality of the power. The
proposed cncrgy meter measures all thc harmonic contcnts of thc power including
the fundamental component. As a result the accuracy of the meter is vcry high even
in the presence of harmonics in the power grid. Having a single chip FPGA dcsign
makes it cost cffective and at the samc timc achieves additional advantages like
less power consumption, less space and components requirements. This also makes
the entire system programmable, reconfigurable and upgradcablc based on
changing requirements at any point in future even after the meters have been
deployed at user premises. The energy meter is further optimized with fast on-chip
memory and parallel path processing so that it will be able to perform all
calculations including voltage measurement, current measurement, power
measurement, phase difference measurement in real-time. An on-chip Fast Fourier
Transform (1'1'1') processor is also designed to calculate and display the third
harmonic distortion. Design synthesis of the meter is done in Veri log Hardware
Descriptive Language (HDL) and the design tool used is Quartus II. The meter is
implemcnted on Altera DE2 board containing Cyclone II FPGA chip. A 16 bit 6
channel simultaneous sampling AID converter AD73360 is used as the only
external component in the meter. The energy meter operates at 3.3 V and draws its
power from the power line. The entire design required 8317 logic elements, 3493
dedicated logic register, 32 embedded multiplier, 4 digital PLL, 388 K memory
units and J MB SDRAM memory. Finally the performance of the meter is
compared with a traditional analog meter. While extreme precision was not
achieved duc to lack of external component precision, the meter was able to
achieve 0.2 class.
