Quantum mechanical modeling and characterization of soft breakdown phenomena CMOS devices with high-k dielectrics

Abstract

With the emergence of the advanced ULSI technology the MOS (Metal- Oxide-Semiconductor) structure has entered the ultra thin gate oxide level. As the device size is scaled down, the reliability of the structure has become a major concern. The abrupt loss of the insulating property of the Si02 is one of the important reasons behind the failure of the MOS device performance. Much work has been devoted to the pre-breakdown degradation of the oxide when subjected to electrical stress. The insulator subjected to the electrical stress, undergoes degradation which eventually accelerates the increase in the leakage current which is termed as Stress Induced Leakage Current (SILC). In recent years, a new failure mode has been identified in ultra thin oxide of MOS devices under high field stress resulting in an abrupt increase in the conduction through gate oxide without causing hard breakdown (HBD). This new mode has been termed Soft Breakdown (SBD). In this work, we formulated a complete quantum mechanical model for NMOS device by solving coupled Schrodinger's and Poisson's equations selfconsistently to demonstrate the SBD conduction for a wide range of applied gate voltage. We simulate the gate leakage current both the fresh oxide and after the soft breakdown condition with the experimental data. The concept of lowering the, barrier height at the soft breakdown spot is introduced here to calculate the soft breakdown current. In this work, a Soft Breakdown spot is characterized in.terms of its barrier height, effective thickness, spot area, electron effective mass, imaginary potential etc. Variation of these parameters is considered to obtain.exp~rimental fit between the experimental and theoretical SBD current. We simulate the model for PMOS device and finally extract the SBD parameters for high-k stack. The SBD spot area in the HfAIOx is 1.4 times higher then the SBD spot area in the Si02•