Abstract:
A self synchronized TR-UWB receiver front-end is designed in this dissertation using model
parameters of IBM® 90nm CMOS technology on industry standard Cadence and Hspice
platforms. Novel circuit topologies are proposed which realize the practical on-chip
implementation of a TR-UWB transceiver. At first, a wideband delay element (WBDE) is
designed with multi staging capacity and monotonic delays which is able to handle very narrow
UWB pulses. It is built in an integrated fashion with low power requirements desirable for onchip
wireless interconnects. A wide range of delays of monotonic nature (100-1000ps) is
achieved by varying the dimensions of the transistors, the power supply voltage, the shunt
capacitances and the number of stages in the delay chain. The WBDE also provides the added
benefit of making the receiver self-synchronizing as the mixer after it no longer needs a separate
template signal. A cascode 21GHz low noise amplifier (LNA) which boosts the weak signal
without degrading the overall noise figure is included in the design. The forward gain (S21) of
the LNA is 9.72dB at 21GHz with 4GHz bandwidth (19GHz - 23GHz). Reverse isolation is
always less than -26.4dB. Input and output matching parameters are -26dB (S11) and -19.5dB
(S22) respectively near the center frequency. Noise figure is 4.4 dB at the center frequency and
the circuit is unconditionally stable. The amplifier consumes 20.76mW of power (including the
bias circuitry) when driven by a 1.2 V power supply. A direct conversion mixer which uses three
differential MOS pairs is analyzed for the ultra-wideband systems. To improve its gain, noise
performance and linearity new techniques like bleeding transistors and resonant inductors are
tried out to compensate for parasitic capacitances. RF and IF frequencies of the RF mixer are 5.1
GHz and 100 MHz respectively, and the radio frequency can be adjusted within the range of 2-
20GHz. A voltage conversion gain of 16.1 dB and a DSB Noise Figure of 8.253 dB have been
achieved with very low power consumption. A high degree of LO to RF isolation (in the range of
-94dB), RF to IF isolation (in the range of -95dB), LO to IF isolation (in the range of -143dB)
and RF to LO isolation (in the range of -6.4kdB) is expected for this design. This mixer achieves
an input-referred IP3 (third order inter modulation product) point of −1.93 dBm and an input
referred 1 dB compression point of -10.67dBm. Along with transient and HB (Harmonic
Balance) analysis, PSS (Periodic Steady State), Swept PAC (Periodic Alternating Signal), Swept
PXF, QPSS (Quasi-periodic Steady State), QPAC, PSP (Periodic S-Parameter), Pnoise (Periodic
Noise), and QPnoise (Quasi-periodic Noise) analyses are performed for the mixer to ensure
optimized performance. A fully symmetric operational trans-conductance amplifier (OTA) based
analog window comparator is used as a novel threshold detector for UWB systems which provides the output stream at a bit rate 0.1 to 1Gbps. During the schematic design phase,
extensive iterations are carried out to optimize transistor sizes. The findings are compared with
results from other standard UWB techniques and the accuracy of the results is also evaluated so
that the design is ready to be added to the industrial process flow. The TR-UWB receiver system
satisfies the gain-noise-linearity requirements of a microwave receiver and will facilitate the
realization of the TR-UWB communication scheme.
