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Surface potential and threshold voltage modeling of pocket implanted asymmetric n-channel MOSFETs

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dc.contributor.advisor Ziaur Rahman Khan, Dr. Md.
dc.contributor.author Naeemul Islam, S.M.
dc.date.accessioned 2016-08-06T05:18:29Z
dc.date.available 2016-08-06T05:18:29Z
dc.date.issued 2012-05
dc.identifier.uri http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3599
dc.description.abstract The use of asymmetric MOSFET has availed seeking new perspective in nanotechnology. There are various difficulties and challenges in pursuit of high functional density in such low dimension. The conventional symmetric long channel MOSFET device often fails to meet up the challenges and that makes the demand of contemplation of asymmetric MOSFET. It has been observed that asymmetry on MOSFET device brings superior control on threshold voltage roll off, drain induced barrier lowering and other short channel effects which are the challenges offered in the low dimension. So analysis and physical reasoning of nano scale MOSFET device is important. This research presents an analytical modeling of surface potential model of nano scale asymmetric n-channel enhancement type MOSFET device. The analytical model of surface potential is further devised to achieve threshold voltage values for corresponding device. An asymmetric MOSFET can be generally described as a planar MOSFET having a laterally non uniform body profile (channel asymmetry) with or without different source or drain regions (source/drain asymmetry). The device under analysis of this work, consists both channel and source-drain asymmetry incorporating retrograde wells. The architecture contains pocket implantation only on source side unlike the popular symmetric configuration of pocket implant on both source and drain side. The absence of pocket implant at the drain side ensures comparatively weaker electric field near the drain. Due to less electric field, the hot carrier injection problem, one of the short channel effects, can be mitigated. The architecture also contains source extension at source side and deep lightly doped drain (LDD) at drain side. Highly doped source extension reduces parasitic resistances and ensures a better drive current performance of the device. On the other hand LDD structure at drain side averts abrupt change of electric field and reduces hot carrier injection effect. The analysis of such sublime device has been performed by solving Poisson’s equation considering appropriate boundary conditions. The analytical model of surface potential and threshold voltage, established by solving Poisson’s equation has been investigated and verified by numerical modeling of the corresponding device in a process simulator. The device performance and underlying physics are analyzed varying a wide range of process parameters. The modeling accuracy is further verified by comparing with the data of manufactured device reported in recent literature. The analytical model shows a good and consistent accuracy with the numerical model data and the data reported in recent literature. en_US
dc.language.iso en en_US
dc.publisher Department of Electrical and Electronic Engineering (EEE) en_US
dc.subject MOSFET en_US
dc.title Surface potential and threshold voltage modeling of pocket implanted asymmetric n-channel MOSFETs en_US
dc.type Thesis-MSc en_US
dc.contributor.id 1009062086 P en_US
dc.identifier.accessionNumber 111130
dc.contributor.callno 623.9732/NAE/2012 en_US


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