Abstract:
Recently reported technique to deposit a suitable gate oxide on InGaAs channel material
has led the researchers to fabricate surface channel InxGa1¡xAs MOSFETs with
a thin channel layer on a metamorphically grown buffer layer. In this type of device,
biaxial strain appears due to the mismatch in lattice parameter between channel layer
and buffer layer. Also, InxGa1¡xAs=InAs MOS HEMT has been successfully fabricated
recently. No systematic study has been found regarding the effect of strain on
device performance of these devices. In this thesis, using self-consistent simulation
technique, a detailed study has been performed to observe the effect of strain on device
performance in these types of devices. Both electrostatic and transport performance
have been taken into consideration. Ballistic transport limit has been calculated
using a 1-D model. This work has revealed some significant performance issues pertaining
to strain in these devices. Also a new technique to extract threshold voltage
in surface channel MOSFET has been proposed. In this technique, the peak of the ratio
of first subband occupancy to the total inversion carrier concentration is identified.
The gate voltage corresponding to the peak is extracted as the threshold voltage. It has
been observed that the threshold voltage is significantly affected due to the change in
strain. Also, the occupancy of the first subband does not remain constant throughout
the gate bias. This suggests that for compact or analytical modeling of the device, contribution
of the higher subbands should be taken into account. For MOS HEMT, it has
been observed that delta doped barrier layer provides better device performance. The
results presented in this thesis reveals some important issues pertaining to the future
generation channel engineering in order to achieve high speed, low power device with
alternate substrate material.
