Design of a low power AES processor

Abstract

The National Institute of Standards and Technology (NIST) announced Rijndael as the new Advanced Encryption Standard (AES) in 2001. After that a lot of researchers are working to improve the performance of AES in three areas; speed, memory size and power. Depending on various applications, the low power consumption criteria has become a great issue in small computing devices like contactless smart card, wireless sensor, small computing devices, RFID etc. This thesis proposes the design of a low power AES processor without sacrificing its security, compactness and throughputs. Novel techniques have been introduced to meet the low power criteria in designing the processor. The proposed design consists of a composite field based design of substitution box (s-box) in the finite field GF (24)2 rather than the original design in Galios Field (28). An optimized s-box is also considered for this architecture. Look up table based implementation for two operations which are multiplicative inverse and multiplication by constant is performed in s-box. The proposed processor also mitigates the glitches that occur for unequal path lengths in the s-box and inverse s-box. To reduce the unwanted paths or glitches from the datapath pipelined structure of 3-multipliers is used. This design does not hamper the security of the AES algorithm. The processor is simulated in Quartus II simulation software in the Altera Cyclone II FPGA family device and analyzed in terms of power consumption for the processor. The performance of the processor are compared to those of other research works and found the superiority over other research works.