Design of a high speed OFDM transmitter and receiver

Abstract

System–on-a-chip (SoC) is now a trend in digital design because it gives a lot of advantages over discrete electronic based product such as higher speed, lower power consumption, smaller size, lower cost etc. Reconfigurable platform such as FPGA, CPLD, and PLD etc. is now being used for designing and implementing SoC due to its low cost and high capacity and tremendous speed. In this project single chip Orthogonal Frequency Division Multiplexing (OFDM) transmitter and receiver has been designed using Verilog HDL. OFDM is a multi carrier modulation technique used in the various digital communication systems like 3G GSM, WiMAX, and LTE etc. The main advantage of this transmission technique is their robustness to channel fading in wireless communication environment. There are many applications of OFDM in communication such as digital audio Broadcasting, asynchronous digital subscriber line (ADSL) and high bit-rate digital subscriber line (HDSL) systems etc. In OFDM, two digital signal processing algorithm Fast Fourier transform (FFT) and Inverse Fast Fourier Transform (IFFT) are mainly involved. The 8- points IFFT/FFT decimation-in-frequency (DIF) with radix-2 algorithm have been analyzed and incorporated in the design. The design has been simulated on the FPGA platform under Altera’s Quartus II environment. Simulation results show that each of the modules of the proposed OFDM is working as desired. The test output achieved from the simulation result of the OFDM has been verified with that of the MATLAB output.