Design of an ASIC for high speed computation of decimal logarithm

Abstract

Logarithm function plays a vital role in all computer systems.With the inclusion of decimal floating point operation in the IEEE754-2008 Standard, a lot of research is going on for developing algorithms and architectures that support computation of decimal logarithm. This project presents the design of an application specific integrated circuit (ASIC) for direct computation of decimal logarithm of a number. A simple but novel technique is introduced in desiging the ASIC. The design is compiled and simulated using Quartus II electronic design automation tool and then implemented on field programmable gate array (FPGA) device. Simulation and implementation results verify the desired functionality of the proposed design. The proposed design is implemented using only combinational circuits and so it will perform all the operation in very high speed. It also outperforms other design proposed by other researchers in terms of power consumption which is inline with the latest trend of the research in ASIC design.