FPGA implementation of an AES processor

Abstract

Information security is now a burning issue in this era. A number of algorithms on cryptography have been proposed in the literatures. However Advanced Encryption Standard (AES) outperforms all other existing techniques for protecting data. AES can be implemented in software or in hardware. The hardware implementation offers high speed and better physical security than that of software implementation. This report presents the design of an AES processor using Verilog HDL and its implementation on FPGA hardware. The simulation results of the processor are also presented to show its proper functionality. The performance of the processor in terms of logic cell, latency and speed is measured and shown in this report. The proposed processor can be used as an Intellectual Property (IP) for developing various security applications.