Abstract:
This project presents the design of a programmable convolutional encoder and Viterbi decoder (CEVD) using Verilog HDL. It is implemented on FPGA platform using coding rate, trellis length as parameter for configuring the chip. High coding rate transmission is reliable but takes more time to decode comparing with low coding rate. Long trellis length causes the Viterbi algorithm to take more time to decode but reliable compare with short trellis length. These combined effects are taken as consideration for design and implementation of the proposed system. Four different CEVD are designed using 1/2, 1/3 coding rate and 4, 15 trellis length. The design is simulated using Quartus II EDA tool and then implemented on the Cyclone II FPGA device. Simulation and implementation results ensure the desired functionality of the proposed design. The proposed CEVD can be used as an intellectual property for designing application specific integrated circuit (ASIC) related to wireless communication.
