Abstract:
The miniaturization of traditional planar Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) becomes quite challenging for very short channel devices as the formation of ultra-sharp source and drain junctions with a high process complexity is needed. Junctionless Field Effect Transistors (JLFETs) are considered promising for the sub-20 nm era due to their constant doping profile from source to drain. They provide a great scalability without the need for rigorously controlled doping and activation techniques as well as reduced short channel effects (SCEs) compared to the conventional MOSFETs. Though a number of analytical and simulation studies based on one-dimensional (1-D) model for Double Gate (DG) JLFETs have been carried out over the past few years but rigorous and accurate two-dimensional (2-D) analytical study on this device is yet to be reported. This work proposes a physically based analytical model of 2-D electrostatic potential in the channel applicable for both symmetric and asymmetric DG JLFETs considering similar and dissimilar gate biased configurations operating in the subthreshold region. The model is derived by solving 2-D Poisson’s equation along the channel while assuming a cubic potential distribution across the silicon thickness using appropriate boundary conditions and 1-D capacitance model. Different device parameters like channel doping concentration, thicknesses of silicon channel, top and bottom gate oxide, gate length, applied drain and gate biases, flat-band voltages of gates etc. are included in this model. To justify the accuracy of the model, Poisson’s equation with the same boundary conditions is solved in the COMSOL Multiphysics using Finite Element Method (FEM) and the obtained results are matched with those of the modeled ones. The obtained results from analytical model is also matched with SILVACO ATLAS simulation results to underpin the validity of this model. The proposed potential model is compared with the reported data available in the literature for short channel symmetric DG JLFET. In order to avoid extensive mathematical complexity numerical techniques by MATLAB is further used to calculate threshold voltage, subthreshold drain current and different SCEs viz. threshold voltage roll-off (TVRO), drain induced barrier lowering (DIBL), subthreshold swing (SS) from the proposed analytical model for different structures of DG JLFETs. A detail comparative study of potential distribution in the channel region for different gate and drain voltages obtained from the proposed analytical model is performed for symmetric and asymmetric DG JLFETs. The effect of bottom gate flat-band voltage of asymmetric structures and bottom gate voltage of dissimilar gate biased structures on the threshold voltage are investigated. Finally a performance comparison of subthreshold behavior i.e. TVRO, DIBL, drain current and SS have been made between symmetric and asymmetric DG JLFETs. Both symmetric and asymmetric DG JLFETs show nearly ideal TVRO (~0V), DIBL (~0mV/V) and SS (~60mV/decade) at the gate length around 50nm which make them good competitors of the conventional MOSFETs for short channel devices.
