Abstract:
Two key challenges for future integrated circuit technology are pushing CMOS beyond its ultimate scaled density and expanding information processing beyond that attainable by CMOS alone, using new devices and architectural approaches. In this regard, quantum tunneling based devices, with unique negative differential resistance (NDR) characteristic show a lot of promise in high speed memory applications. However, practical implementation of such memory devices is challenging due to low peak to valley current ratio (PVCR) in Si based NDR devices and incompatibility of III-V material based NDR devices with Si technology. In this respect, possibility of novel resonant tunneling device showing NDR behavior based on emerging material such as graphene needs to be explored. In this thesis, a novel double quantum well resonant tunneling negative differential resistance device based on intrinsic armchair graphene nanoribbon (A-GNR) is proposed. Desired device characteristics are calculated from self-consistent solution of three-dimensional Poisson‟s equation and non-equilibrium Green‟s function (NEGF) based transport equation with atomistic resolution. This device shows promising results including the NDR effect at very low bias, at 0.12V, with peak current of 1.78μA and peak to valley current ratio of ~20. Effect of top gate and back gate potential on the NDR characteristic is also analyzed. In similar approach, a complementary (pull up) NDR device is designed and the performance of a source coupled NDR device pair as a static memory latch is investigated. Results shows, bi-stable operation in such memory latch is ensured for bias voltage range of 0.26 V to 1.1 V. A graphene nanoribbon field-effect transistor (GNR-FET) with low leakage current (~1.3 nA) and high ON/OFF ratio (~104) is designed to be used a access transistor in memory addressing. Finally, an all graphene tunneling random access memory (TRAM) cell architecture is proposed with GNR-NDR device pair in conjugation with GNR-FET. Different performance matrices of the TRAM e.g. READ access time of 0.7 ns and WRITE access time of 0.43 ns are obtained through composite modeling of the device. The memory cell has ultra high bit density (as the cell area is ~112.2 nm2) and has a static power dissipation of 45 nW. All these findings point toward the fact that the proposed all graphene TRAM cell is likely to be the key candidate for the future high-density, high performance and low power memory systems.
