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Design of a hummingbird crypto asic implementing bist technique

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dc.contributor.advisor Ali, Dr. Md. Liakot
dc.contributor.author Azizul Haque, Md.
dc.date.accessioned 2017-07-22T04:58:11Z
dc.date.available 2017-07-22T04:58:11Z
dc.date.issued 2016-03
dc.identifier.uri http://lib.buet.ac.bd:8080/xmlui/handle/123456789/4540
dc.description.abstract There are several emerging areas in which highly resource constrained devices are interconnected, typically communicating wirelessly with one another, and working in concert to accomplish some task. Examples of these areas include: sensor networks, healthcare, distributed control systems, the Internet of Things, cyber physical systems, and the smart grid. Security and privacy can be very important in all of these areas. Because the majority of current cryptographic algorithms were designed for desktop/server environments, many of these algorithms do not fit into the constrained resources. If current algorithms can be made to fit into the limited resources of constrained environments, their performance is typically not acceptable. Here comes in the Lightweight Cryptography. Many research works have been going on this topic. Among them, Hummingbird is a new ultra-lightweight cryptographic algorithm targeted for resource-constrained devices like RFID tags, smart cards, and wireless sensor nodes. The efficiency of the algorithm has been verified in software solution for a wide range of embedded applications. In this paper, we describe FPGA implementation with both software simulation as well as HW implementation of Hummingbird algorithm on Altera Platform. Again testability of a complex chip is of prime concern now a days. It consists of IC design techniques that add the features to test the designed hardware and ensure the chip is free from defects and will function correctly. Because of its convenience and less expensiveness over ATE, Built-In-Self-Test (BIST) is a widely used technique for this purpose. In this project design of a Hummingbird Crypto ASIC implementing BIST technique is proposed. In this design LFSR is used to generate pseudorandom test pattern and Signature Analysis is used as a Data Compression Technique to implement BIST for multiple test counts. The proposed Crypto ASIC is simulated in Quartus II simulation software in the Altera Cyclone II family device as well as hardware implementation done in Altera DE2 board and performance is analyzed and compared with the other research works on Hummingbird implementation. en_US
dc.language.iso en en_US
dc.publisher Institute of Information and Communication Technology (IICT) en_US
dc.subject Data protection en_US
dc.title Design of a hummingbird crypto asic implementing bist technique en_US
dc.type Thesis-MSc en_US
dc.contributor.id M 1009312003 en_US
dc.identifier.accessionNumber 115048
dc.contributor.callno 005.8/AZI/2016 en_US


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