Abstract:
This report presents the design of an efficient low power decimal logarithmic converter. The technique is based on shift operation along with a precision unit which is used to prevent unnecessary scan of full memory table. Precision level is user programmable. It does not require multiplication or division circuitry which in turn makes it low power. Proposed decimal logarithmic converter has been designed using Verilog HDL and then compiled and simulated using Altera provided Quartus II compiler and Modelsim simulator. The synthesis results show that the proposed design outperforms all the existing proposed decimal logarithmic converters by other researchers.
The calculation is based on memory. Some predefined value and there log value are stored in memory and by using that value we calculate the logarithm of any value. Another feature which is called precision unit is used for controlling unnecessary scan of memory table. According to input of precision value the algorithm calculates logarithm value. Thus by increasing of precision value we can increase accuracy of the result.
This algorithm does not need multiplication circuitry and required very low memory thus it makes the algorithm very low power.
