Abstract:
Memristor is a newly fabricated device which is becoming very popular among the researchers for its non-volatility, nanometer size and good switching behavior. In this work- memristor-MOS hybrid architecture based quaternary memory array design with complete read write technique has been developed. Each individual cell of the large memory array system contains only one memristor and a cell selection transistor and is able to store two bits of memory in the single cell. The proposed writing technique for this design is data erasing based which reduces circuit complexity by avoiding feedback read-based writing technique. The write circuit of the proposed design consists of a simple transmission gate and is common for the whole memory array. As a single cell stores two bits of data or in other words 4 different states (00, 01, 10, 11), the writing time is larger than conventional memory circuits. The read mechanism for this design is simple voltage division based and the read circuit has only a memristor and read enabling transistor. A complete 16×16 quaternary memory array with necessary peripheral read-write circuit has been simulated in LTSPICE for the verification of the proposed design. Further analysis has been done to prove that the proposed design shows superiority in terms of compactness, energy consumption, acceptable noise margin and simplicity in operation.
