Analytical model and performance analysis of graded channel dual material double gate junctionless field effect transistor with high-k spacer

Abstract

The continuous downscaling of chip size and dimension have led to the innovation of newer, cheaper and more efficient transistors since its first invention in 1947. As predicted by More Moore scaling, the transistor’s gate length will be reduced to 5 nm by 2024 and new device structures other than conventional MOSFET and finFET need to be introduced to improve the short channel characteristics and device performance. The researchers have suggested various emerging and potential device structures like tunnel field effect transistor (TFET), junctionless field effect transistor (JLFET), spin field effect transistor (spin-FET), negative capacitance metal oxide semiconductor (NCMOS) etc. In this thesis, the presented work is dedicated to JLFET. In recent years, many research papers and publications have already been done on diverse structures of both symmetric and asymmetric JLFET such as, nanowire, double gate, dual material, stack-oxide, graded channel, inclusion of high-k and dual-k spacer etc. In this thesis, a two-dimensional analytical model for graded channel dual material double gate JLFET with high-k spacer (GC-DM-DG-JLFET-SP) has been proposed by solving two-dimensional Poisson’s equation, assuming cubic potential distribution across the channel and considering fringing field effect in spacer region. Though previously, simulation-based performance analysis on similar device has been done, no publication has been reported yet on the development of its two-dimensional analytical model. The derived analytical model of surface potential has later been verified with the published simulated result. After the verification, surface potential, drain current, different short channel characteristics like drain induced barrier lowering (DIBL) and subthreshold swing (SS) and different performance parameters and figure of merits like on/off current ratio, transconductance (g_m), transconductance generation factor (g_m⁄I_ds ), drain output conductance (G_D), intrinsic gain (A_V0) and early voltage (V_EA) of GC-DM-DG-JLFET-SP have been compared with those of uniform channel dual material double gate junctionless field effect transistor with high-k spacer (UC-DM-DG-JLFET-SP). The presented device GC-DM-DG-JLFET-SP shows higher on/off current ratio, better suppression of DIBL and SS and improved G_D while causing degradation of g_m and V_EA and very slight degradation of A_V0. All performance analysis and comparisons have been done using MATLAB and calculations of performance parameters have been done numerically using the developed two-dimensional analytical model of potential distribution to avoid mathematical complexity.