Phonon scattered electron transport calculation of junctionless nanowire transistor by a computationally efficient atomistic approach

Abstract

In this thesis, electronic transport characteristics of Junctionless Nanowire Transistor (JNT) in presence of phonon scattering has been studied. JNT is a novel electronic device, which has no distinct p-n junction and no doping concentration gradients in its structure. As the channel length of MOSFETs scales down, the formation of ultra-shallow source/drain junctions poses difficult fabrication challenge. The JNT overcomes this difficulty as it has no p-n junction. The device contains a doped Silicon channel region surrounded by two Poly gate structures on opposite directions, separated by an oxide layer on each side. As gate voltage is increased, the induced depletion region reduces, and as voltage exceeds threshold, the channel conductance commences. For voltage over flat-band, the device operation switches from depletion to accumulation mode. The current-voltage characteristics of the device closely resemble that of MOSFET. The device, free from doping gradient optimization constraints, can support further scaling down of the device structure than traditional FETs. The device also exhibits better non-ideal short channel and subthreshold characteristics, along with superior high temperature operations. Instead of conventional effective mass approach the quantum mechanical atomistic tight binding method has been used in this thesis. The effect of phonon scattering on electronic current has also been studied. In this thesis, the atomic scale calculations were performed in Python scripting via QuantumATK software. Electronic band structure, transmission spectrum and projected local density of states were observed. The phonon band structure, phonon density of states and phonon transmission spectrum were also observed. The elastic and inelastic component of current were analyzed. The inelastic current distribution due to various phonon modes was explained. Then the total current of the device with varying gate and drain voltage was calculated. The drain current vs gate voltage was evaluated by varying oxide thickness, channel thickness, channel length, doping concentration, and channel material crystal orientation. Finally, the simulation approach was verified by comparing with other results.