Design optimization of processvariation tolerant spoof surface plasmon polariton interconnect for chip-to-chip communication

Abstract

Abstract We are now at ‘Beyond the Moore’ era where design bottleneck lies in the interconnect design instead of transistors, which has been termed by many as tyranny of interconnects. About the two major choice of interconnects, it has been shown that for small intra-chip communication, electrical interconnect is the best option, while optical interconnect is better as long distance interconnects. The distance 0.1 cm - 10 cm is known as the last centimeter barrier where neither optical nor electrical interconnect performs well. So, we need an alternative solution for this region. This is where the Spoof Surface Plasmon Polariton (SSPP) interconnect is an attractive choice for some of its desirable electrodynamic characteristics. SSPP interconnect was proposed very recently and there are many different aspects of it yet to be explored. Still, there is no optimized design for SSPP interconnect. We have optimized the interconnect design and Vivaldi antenna (opto-electric converter and vice versa). But the very first issue that rises is how does this interconnect perform in the presence of fabrication process variation, given that SSPP characteristics strongly depend on pattering. In this study, this issue was explored in detail. The effect of process variation on SSPP interconnect was studied extensively. Then a compensation circuit was designed using current mirror technique to restore the signal to its original form. The circuit design was validated by reconstructing the distorted signal and also by performing cross-correlation, showing high level of similarity between original and reconstructed signal. It was also shown that the designed circuitry works even for a long bit sequence. Finally, everything was put together to design a process variation tolerant data transmission system using SSPP interconnect.