Analytical modeling of electrostatic and transport phenomena in inversion-type inGaAs nanowire MOSFET

Abstract

The prime motivation driving the semiconductor industry to fabricate devices of extremely reduced dimension is the innovation of novel technologies that enable manufacturers to create transistors in the sub 22-nm node, where short-channel effects (SCE) become a barrier for silicon technology in planar field effect transistors. Researchers are now moving to multi-gate structure that offer enhanced gate control over short channel effects to the highest degree. Particularly, gate-all-around (GAA) nanowire transistor have shown tremendous success in terms of improved electrostatic control but at the expense of mobility degradation at the surface due to oxide charges present at the oxide-semiconductor interface. Integration of III-V materials in the channel instead of silicon provides a viable solution for this dilemma, the bottleneck being the availability of a suitable native oxide unlike SiO2 on silicon. Previous reports on InGaAs nanowire MOSFETs include electrostatic characterization and transport modeling in uncoupled mode space (UMS) approach both of which rely on quantum mechanical simulation that is computationally expensive. This work presents an analytical investigation of the electrostatic and drain current model for symmetric short channel InGaAs gate-all-around MOSFET valid from depletion to strong inversion using a continuous expression. The development of the core model is facilitated by the solution of quasi 2-D Poisson equation in the doped channel, accounting for interface trap defects and fixed oxide charges. Correction to short channel effects such as threshold voltage roll-off, drain induced barrier lowering and subthreshold slope degradation are later introduced, complemented with channel length modulation, velocity saturation and mobility degradation from surface roughness, leading to an accurate mobile charge density for electrostatic capacitance-voltage and transport characterization. A threshold voltage model is presented for long channel gate-all-around device that utilizes the well-known double derivative method, which is crucial for determining threshold voltage roll-off with scaling of transistors. The effect of physical process parameters like fin width, oxide thickness and channel length scaling are thoroughly investigated in both on and off state of the transistor. The robustness of the model is reflected from the precise match with published experimental reports in the literature. An Ron of 1160 Ω.µm is obtained from output characteristics and switching efficiency (ratio of maximum transconductance to subthreshold slope) improvement of 2.5 times is estimated from incorporating high-κ dielectric into the GAA transistor. Numerical 3-D simulations from TCAD corroborates the validity of the proposed model in all regions of operation.