Abstract:
This report presents the design of a Built-In Self-Test (BIST) implemented Advanced Encryption Standard (AES) crypto-processor Application Specific Integrated Circuit (ASIC). AES has been proved as the strongest symmetric encryption algorithm declared by USA Govt. and it outperforms all other existing cryptographic algorithms. AES can be implemented in two approaches: software and hardware. The software implementation offers lower speed performance and limited physical security than that of hardware implementation.Due to enormous speed and security performances, now a lot of research fordesign of AES processor chipis reported in the literature. Nowadays
testability of a complex chip is a burning issue. This research presented in this reportintroduces a solution of the testability problem for the AES crypto processor chip implementing mixed-mode BIST technique which is hybrid of pseudo random and deterministic technique. In designing the BIST implemented AES ASIC, the AES algorithm is simulated using JAVA software and tested using the NIST provided input and output data. Then, the ASIC is designed using Verilog Hardware Description Language (HDL). The BIST circuitry consists of a test manager, Linear Feedback Shift Register (LFSR), Output Response Analyzer (ORA), memory to store seed for pseudo random pattern, seed for deterministic test pattern, test length and golden signature integrated into the ASIC. In test mode of the ASIC, the test manager enables the LFSR and initializes it with seed value from the memory and generates desired number of pseudo-random test patterns which are applied to the AES ASIC and outputs are compressed through the ORA and then the test manger switches to the deterministic mode in which it generates deterministic test pattern using the seed value stored in the memory and apply to the AES ASIC and compress it accordingly. Finally, signature is generated in the ORA which is compared with that of golden signature stored in the memory. If both the signatures match each other, then the ASIC is ensured as fault free; otherwise it is faulty. The HDL design of the Crypto ASIC is simulated using ModelSim EDA software. The simulation results show that the BIST implanted ASIC is working as per desired functionalities. In the future, the ASIC can be implemented into FPGA hardware and its performance in terms of logic gates, speed and power can be measured.
