Abstract:
Reverse engineering is a burning issue in integrated circuit (IC) design and manufacturing. It results in revenue loss of billions of dollars every year. Through reverse engineering process, an attacker can easily find out the functionality of a chip using Scanning Electronic Microscopy (SEM) image processing techniques. Several researches have been done to combat this issue in the material level by changing the doping concentration and relevant techniques. In this work, a technique has been implemented in the physical design level to reduce the recognition of a circuit functionality through image processing methodology. Attacker will see similar layout structure or similar images for the universal logic gates. And, using these universal gates we can design any other logic gates and the whole standard cell library as well. For better output, besides physical design modifications, dummy/true contact based technique has been implemented. The library contains different camouflaged primitive gates developed by combination of usingmetal routing technique and true/dummy contact technique. In IC design industry, it is required to compromise additional area, power consumption, delay and relevant factor while implementing IC camouflaging techniques. This works results in increase of the total area by about 17.37% and 1.357ps delay. To implement and verify these things, firstly, universal gates NAND and NOR have been designed applying proposed techniques in Cadence Virtuoso platform. Then, a bigger logic gate, XOR has been designed using both convenient gates and camouflaged gates. Finally, a comparison has been shown what changes are found after implementing these techniques. The whole design has been implemented in 90nm process technology.
