Abstract:
This thesis focuses on designing robust and reliable fault testing methods using oscillators to detect transistor stuck-on (TSON) faults in submicron CMOS circuits. Simulations are performed in Cadence Virtuoso platform using 90 nm technology models. There are several structures for voltage controlled oscillators (VCO), among which the single-ended ring oscillator (SERO) structure is utilized for its superiority in terms of power penalty and manufacturability. The conventional structure has been modified with split-load technique for dual-mode tuning to facilitate greater control in frequency regulation. Meanwhile, the low power requirement of the circuit is maintained through device sizing. While considering the effects of parasitic capacitances, the proposed architecture provided the maximum tuning range when compared with other presented works in literature. Next, the frequency response of the oscillator has been investigated as a function of the controlling parameters tuning voltages, number of stages in the ring, and transistor width ratio to derive an empirical model for the operating point. Unlike the existing approximate models which only apply for the conventional SERO circuit, the frequency model in this work will assist the designer to accurately set the desired operating point. Finally, the SERO architecture with its load adaptation has been utilized to propose two fault-testing methods where the oscillator functions as current- and voltage-controlled oscillators, respectively. The test schemes exploit triggered output oscillations during the presence of a fault in the circuit under test (CUT). Computational ease and system reliability are improved by avoiding average quiescent current calculation in the IDDQ method and indeterminate voltages of the logic voltage method. The proposed testing schemes remain more effective in high-leakage CMOS regime through threshold regulation achieved by multimode tuning of the split-load SERO and mirror device sizing, circumventing complex circuitry compared to built-in-current-sensor (BICS) protocols for on-chip fault detection.
