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Detection of recycled field programmable gate arrays using clustering algorithm

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dc.contributor.advisor Ali, Prof. Dr. Md. Liakot
dc.contributor.author Tarique, Tanvir Ahmad
dc.date.accessioned 2023-11-25T09:33:22Z
dc.date.available 2023-11-25T09:33:22Z
dc.date.issued 2022-11-28
dc.identifier.uri http://lib.buet.ac.bd:8080/xmlui/handle/123456789/6500
dc.description.abstract Field Programmable Gate Array (FPGA) is a popular electronic component used in many applications due to their cost-effectiveness, competitive performance, and power efficiency. However, some third-party vendors in the semiconductor industry collect used FPGAs and refurbish them to sell as a new, posing security and reliability issues for mission-critical systems. Researchers have proposed various methods to detect recycled FPGAs, including ring oscillator-based delay analysis or fingerprint (FP) analysis using supervised machine learning (ML) technique. However, these methods require a large amount of data and time, which is not practical due to the rapidly changing technology and large number of FPGAs in the industry. Unsupervised machine learning approaches require less data but still require a significant amount of comparison calculations to achieve high accuracy, which is costly and time-consuming. Finding a faster and cheaper solution to this problem is necessary.Fresh FPGAs have different FP patterns than that of recycled FPGAs. This property has been used by other researchers for classification of recycled FPGAs from fresh FPGAs. However huge computation is required in this case. This thesis has introduced a novel technique to reduce the computational complexities using the property of symmetricity of the structure of FPGAs. Due to systematic process variation within the FPGA, the neighboring combinational logic blocks (CLBs) of FPGAs have similar or symmetrical array structures, leading to similar FPs in the neighboring logic blocks. This symmetrical property has been exploited for detecting recycled FPGAs using Clustering Algorithm (CA)-based anomaly or outlier detectionscheme with K-means++ techniquewhich analyzes the neighboring ring oscillator (RO) frequencies’ symmetrical or similarity information.The proposed symmetry analysis method efficiently detects all the recycled FPGAs through outlier detection, achieving 92% accuracy in a very short period of time with around 41% less computations compared to the previous unsupervised ML-based method. In future, research can be carried out to improve the accuracy using more reduced computations. en_US
dc.language.iso en en_US
dc.publisher Institute of Information and Communication Technology (IICT) en_US
dc.subject Algorithms en_US
dc.title Detection of recycled field programmable gate arrays using clustering algorithm en_US
dc.type Thesis-MSc en_US
dc.contributor.id 1017312012 en_US
dc.identifier.accessionNumber 119372
dc.contributor.callno 006.31/TAN/2022 en_US


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