Abstract:
Advancement of technology exerts enormous pressure on scaling of devices with a view of improved performance. The scaling of device technology faces significant challenges to control the short channel effects (SCE) and limits the further shrinkage of device size. A number of new architectures have been reported to mitigate these effects. Double gate MOSFET is a promising candidate because of its SCE handling capability. The gate electrodes with more than one material with the different work functions have better control over SCEs. In a Triple Material Double Gate MOSFET, both gate electrodes are composed of three different materials which screen the effect of drain on the source-channel barrier and suppress DIBL (Drain Induced Barrier Lowering). In device of sub-100 nm regime, charge sharing and DIBL effect become very severe. To overcome this issue, halo doping is used i.e., substrate doping is increased selectively near the depletion region. To deal with leakage current, inclusion of high k dielectric has been proved effective. The combined advantages of gate and channel engineering techniques can be achieved in symmetric halo doped gate stacked triple material double gate MOSFET. In this work, a two dimensional analytical model of channel potential, threshold voltage and drain to source current of a triple material double gate double halo gate stacked MOSFET has been developed. Two dimensional Poisson’s equations with proper boundary conditions have been solved to obtain the channel potential considering parabolic approximation. For accurate modeling of the device, bias dependent inner fringing capacitance and effective surface charge have been considered. Basic drift-diffusion equation has been used to model the drain to source current. Mid-channel potential of the device has been used instead of surface potential in the current modeling considering the fact that the punch-through current is not confined only to the surface in a fully depleted MOSFET. Thus, an expression of pinch-off voltage has been derived for modeling the drain current in saturation region accurately. Channel length modulation effect has also been included in the model which lifts up the positive slope in the current voltage characteristics in the pinch off region of a MOS device in deep submicron level. The device performance has been analyzed with the variation in device parameters, such as channel length, channel thickness, doping profile etc. Various short channel effects like drain induced barrier lowering, gate leakage, threshold voltage roll-off have also been investigated. This structure shows excellent ability in suppressing various short channel effects. The analytical model of the device will give a deeper insight of the device physics and characteristics. Finally, the proposed model results have been validated against the data obtained from a commercially available numerical device simulator.
