Efficient error correction scheme for memristor-based memories

Abstract

Memristor-based memory is an emerging technology that may replace conventional memory devices due to their compact size, higher density, lower power consumption, faster operating time, non-volatile property, and suitability to act as a multi-level memory cell. Soft error immunity is one of the most important qualities which categorizes one memory device as better than another. Therefore, a well-organized and effective soft error-correcting method is required to enhance the reliability of memristor-based memory. In memory systems, the single error correction-double error detection (SEC-DED) code is mostly used to detect and correct soft errors. Memory capacities are increasing which makes memory devices more compact. Therefore, the double, triple, or more-bit soft error problems are also increasing. The performance of the SEC-DED code has been reduced due to its unsatisfactory error correction coverage. The existing error correction coding (ECC) technologies, BCH (Bose, Ray-Chaudhuri, and Hocquenghem), Golay, and HVD (Horizontal-Vertical-Diagonal) codes for multiple-bit errors detection and correction, have lower coding efficiency. In this thesis, an efficient error-correcting technique has been proposed to tolerate soft errors in memristor-based memories. A new scheme named HV-SEC-DED for error correction up to 3 bits that is developed from the SEC-DED code and includes horizontal and vertical check bits. This method can be applied to any sized dataword in the memristor-based memory. A fault injector circuit has also been designed to create any single, double, or triple-bit error in the dataword. This method has been tested and proven by injecting all possible errors up to three bits into the 32-bit, 64-bit, and 128-bit datawords. Matlab code and a Simulink model have been developed for implementing the proposed method in memristor-based memory. The proposed HV-SEC-DED (64) method has 24.48%, 26.56%, and 10.93% lower bit overhead compared to the Golay, BCH, and HVD (64) error correction methods, respectively. The code rate of the proposed method also increases as the number of data bits increases. This method will assist in the development of an efficient soft error-tolerant memristor-based memory system.