Abstract:
The Content Addressable Memory (CAM) is a crucial circuit element in high-speed search engine, data base engine, network switch, artificial intelligence, neural network design etc. The Ternary Content Addressable Memory (TCAM) provides more flexibility by adding a wildcard option.Multiple (12~16) transistors are required in conventional CMOS-based TCAM which results in large area and high power consumption. New emerging device,memristoris being explored to find solution for this area and power limitations.In this dissertation, a memristor based ternary memory cell is designed using the variable resistance characteristics of memristor. A hybrid CMOS-memristor128X128 MTCAMis developed usingthe designed ternary memory cell.
The ternary memory cell is designed with only two memristors connected in anti-serial position. The cell provides three different states (levels) to store three different bits. One MOS transistor is included in the cell to control the access operation. A 2T2M MTCAM cell is formed by adding a 2nd MOS transistor which reads data during the search operation. Incorporating ternary cell in place of 2 binary cells reduces the peripheral wiring approximately by a factor of 2. Besides, write lines and search lines are merged together. A 128X128 MTCAM is presented with necessary match line segmentation technique and appropriatescheme for write/search operation. SPICE simulations were performed using 65 nm TSMC high threshold MOS model parameters.The search time was found 0.75 ns for 1-bit mismatch. The search energies were 0.866 fJ/bit/search and 0.691 fJ/bit/search for mismatch and match conditions respectively. The write times were varied by ±10% to ensure the robustness of the design. The robustness was further verified with Fast and Slow corner simulations. 750 Monte Carlo simulations with ±10% variation of memristor and transistor parameters were performedto verify the reliability. Parasitic RC components were analysed using Cadence Virtuoso Layout-XL and Quantus QRC extraction tools.The pipelining technique of match lines may be applied to add more segments for higher word lengths with an additional 80 ps delay contributed by each 32 bit segment.
