High performance NVRAM circuit design using memristor-mos hybrid architecture

Abstract

Scaling conventional SRAM technologies with respect to number of transistors is a big challenge and volatile memory nature of this technology is one of the biggest deficiencies. A new Memristor-MOS hybrid architecture based RAM structure has been proposed in this thesis which consumes less power and achieves nonvolatile operation (NVRAM) with less number of transistors. The thesis contains the operating procedure and the simulated results of proposed two transistors and two memristors NVRAM using TSMC 180nm CMOS technology simulated in ORCAD PSPICE 9.2. Memristors cover very little area and with only two transistors as opposed to six transistors of conventional SRAMs, the area is substantially reduced by 20.5 times. The proposed NVRAM operated with energy per cycle which is ~40 times smaller than conventional SRAMs. Though the write cycle time is higher but is still comparable, and the read cycle time is slightly lower than the conventional 6T SRAM cell. Again memristors give the circuit non-volatility which is a vital characteristic for any memory circuit. With these advantages our proposed cell can prove to have a very promising future in the field of computer memory.