Abstract:
The demand for solid-state circuit breakers (SSCBs) in modern direct current (DC) power systems is steadily increasing due to their rapid switching capability, high effi- ciency, and reliable fault interruption. In particular, low-voltage DC (LVDC) systems used in residential microgrids, data centers, electric vehicles, and renewable energy sys- tems require advanced protection mechanisms that can handle diverse fault scenarios with precision and speed. Traditional mechanical breakers fall short in meeting these expectations due to slow response times, contact wear, and arcing issues. The existing SSCB topologies, although superior in speed and control, face several critical chal- lenges, including high conduction losses, bulky heat sinks, complex driving circuitry, reliance on auxiliary power supplies, and vulnerability in the presence of parasitic pa- rameters. To address these limitations, this study proposes a novel thyristor-assisted SSCB topology that utilizes a silicon-controlled rectifier (SCR) as the main switch and a single enhancement-mode metal–oxide–semiconductor field-effect transistor (MOS- FET) as the auxiliary turn-off switch. Notably, the design operates autonomously under fault conditions without any auxiliary power supply. At fault condition, the gate-to- source voltage of the MOSFET exceeds the threshold and creates an alternate low- impedance path for the fault current. As a result, the SCR loses its holding current, causing it to turn OFF. Simulation and analytical studies demonstrate successful in- terruption of fault currents up to 62.15A with a fault clearing time below 3ms, and the breaker remains functional even under slow-rising faults with ramp rates as low as 0.8A/ms. The design achieves 97.5% energy efficiency at a 3A nominal current. It also demonstrates inverse time-current characteristics and low sensitivity to parasitic el- ements. Additionally, the design incorporates an inherent low-pass filtering action that improves fault detection accuracy by filtering switching transients. A hardware proto- type has been developed for a 10V/1A system and validated experimentally. Results show a strong correlation with simulations, with measured peak fault currents of 6.4A and fault clearing within 3ms. Compared to state-of-the-art thyristor-based SSCBs, the proposed design achieves a 30–50% cost reduction based on component count while maintaining reliable performance under various fault conditions. These results position the proposed SSCB as a practical and cost-effective solution for LVDC protection.