Modeling electrostatic properties of strained-Si on SiGe MOS devices

Abstract

Electrostatic properties of deep submicron strained-Si (SS)/ Sil_xGex (SiGe) n and p type MOS devices on (100) substrate have been studied under inversion gate voltage bias. Influence of strain on threshold voltage, gate capacitance and direct tunneling current has been modeled using a quantum mechanical (QM) approach. In addition, the threshold voltage is calculated with the help of a derived semiclassical model. In the QM model, potential profile has been calculated by solving the Schriidinger's and Poisson's equation self-consistently. During the selfconsistent calculation wave function penetration int the gate dielectric has been considered. Schriidinger's equation has been solved by the method of Green's function formalism. The effect of dielectric constant change across SS/SiGe interface has been taken into account while solving the Poisson's equation numerically. Threshold voltage has been calculated based on the definition of equal current drive. It has been found that, in strained devices, threshold voltage reduces from that of unstrained devices. The reduction increases with increasing Ge-mole fraction (x), decreasing SS thickness (tsi) and decreasing doping density. Moreover, consideration of SiGe dielectric constant further reduces the threshold voltage under strain. Inclusion of this effect has explained the mismatch between experiment and existing QM model. It has been also found that below a certain x and beyond a certain tsi, the rather complex quantum mechanical model can be replaced by the derived simple semiclassical model in threshold voltage calculation. Results of C-V calculation has shown that for pMOS devices strained C-V characteristics differs from .that of the unstrained one not only in threshold voltages but also in their shapes. The presence of a buried channel in SiGe near the SS/SiGe interface in pMOS is responsible for this difference. The degree of difference increases for higher strain, thinner SS layer and lower doping density. This difference is more prominent at moderate inversion than at high or low inversion level. Finally, tunneling current in SS-nMOS devices has been found to . decrease with increasing x to increase in electron affinity. In SS-pMOS devices, due to nonmonotonic change in SS bandgap, tunneling current shows both an increasing and a decreasing trend depending on x.