Abstract:
Modeling of charge quantization and Capacitance-Voltage (C-V) characteristic of ultra
thin Double Gate (DG) MOSFET in deep submicron regime is studied in the presence of
interface states. Self consistent modeling of double gate MOS inversion and
accumulation layers have been performed by solving both Schrodinger's and Poisson's
equations. A new solver based on Finite Element Method has been developed for the
solution of both Schrodinger's and Poisson's equations that is much faster and more
efficient than existing Schrodinger-Poisson solvers. It has the compatibility of analyzing
both symmetric and asymmetric DG MOSFET structures. The developed numerical
solver has been applied to fully depleted n-MOS and p-MOS DG MOSFETs to analyze
electrostatics such as, inversion and accumulation layer charge density, surface potential,
amount of interface trapped charges. Using these electrostatics, the C-V characteristics of
the devices have been revealed which are found to be in accordance with reported data.
Finally, the effect of interface states is incorporated in the C-V profile. It has been shown
that the effect of interface states on C-V characteristic varies from low to high frequency
operation. Interface trapped charges increase the device capacitance at low frequency and
decrease it at high frequency. Also the degree to which interface trapped charges affect
the capacitance, is also higher during low frequency operations. Simulation results show
that increased oxide thickness amplifies the effect of interface trapped charges on device
capacitance, but variation in silicon thickness or substrate surface orientation don't have
any significant influence on the effect of interface states on C-V profile.
